1. Field of the Invention
The invention relates to an electrostatic discharge (ESD) protection, and more particularly to an ESD protection of a high voltage pin for a low voltage process.
2. Description of the Related Art
Electrostatic discharge phenomenon will cause damage to semiconductor devices and affect normal functioning of integrate circuits (IC). Thus, it is necessary goal for IC designers during the design stage to enhance ESD protection of an IC to increase ESD sensitivity.
Recently, more and more ICs can operate with lower operating voltages, such as operating voltages of typical logic circuits, i.e. 5V, 3.3V, 2.5V and 1.8V etc., due to rapid advancement of low voltage (LV) manufacturing technology. However, for certain products which have particular application requirements, certain pins for an IC require operating at higher voltages, i.e. 7V, 8V, 9V and so on. Voltage substantially greater than 5V but not belonging to a typical high voltage (HV) range, is medium voltage (MV).
For ICs, malfunction will occur in LV devices when an MV is applied to the LV devices. In this situation, the LV device functions will be false since the LV ESD protection circuit is unable to protect pins operated at MV. Therefore, an MV ESD protection circuit for LV processes is needed.